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simplifying system integration tm 73m1903c evaluation board user manual june 12 , 2009 rev. 2.0 um_ 1903c _0 30 downloaded from: http:///
73m1903c evaluation board user manual um_1903c_030 2 rev. 2.0 ? 2009 teridian semiconductor corporation. all rights reserved. teridian semiconductor corpo ration is a registered trademark of teridian semiconductor corporation. simplifying system integration is a trademark of teridian semiconductor corporation. all other trademarks are the property of their respective owners. teridian semiconductor corporation makes no warranty for the use of its products, ot her than expressly contained in the companys warranty detailed in the teridian semiconductor corp oration standard terms and conditions. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any ti me without notice and does not make any commitment to update the information contained herein. accord ingly, the reader is cautioned to verify that this document is current by comparing it to th e latest version on http://www.teridian.com or by checking with your sales representative. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 92618 tel (714) 508 - 8800, fax (714) 5 08 - 8877, http://ww w.teridian.com downloaded from: http:///
um_1903c_030 73m1903c evaluation board user manual rev. 2.0 3 table of contents 1 introduction ................................................................................................................................... 5 1.1 safety and esd notes .......................................................................................................... 5 1.2 evaluation board host interfaces .......................................................................................... 5 2 system description ....................................................................................................................... 6 2.1 mafe interface ..................................................................................................................... 7 2.2 73m1903c register map ...................................................................................................... 9 2.3 73m1903c system initialization ............................................................................................ 9 2.4 typical sample rate settings ............................................................................................. 11 3 hardware description .................................................................................................................. 12 3.1 board settings: jumpers and connectors ........................................................................... 12 3.2 board physical and operating information .......................................................................... 16 4 73m1903c evaluation board schematics, pcb layouts and bill of materials .......................... 17 4.1 sch ematic ........................................................................................................................... 17 4.2 pcb layouts ....................................................................................................................... 18 4.3 bill of materials ................................................................................................................... 21 5 ordering information ................................................................................................................... 23 6 related documentation ............................................................................................................... 23 7 contact information ..................................................................................................................... 23 revision history .................................................................................................................................. 23 downloaded from: http:///
73m1903c evaluation board user manual um_1903c_030 4 rev. 2.0 figures figure 1: 73m1903c evaluation board ..................................................................................................... 5 figure 2: 73m1903c evaluation board block diagram ............................................................................. 6 figure 3: 73m1903c in master or slave configuration ............................................................................. 7 figure 4: 73m1903c daisy chain configurat ions ..................................................................................... 7 figure 5: mafe timing diagram .............................................................................................................. 8 figure 6: serial data timing .................................................................................................................... 8 figure 7: 73m1903c evaluation board jumpers and connectors ........................................................... 12 figure 8: 73m1903c evaluation board pcb dimensions ....................................................................... 16 figure 9: 73m1903c evaluation board electrical schematic .................................................................. 17 figure 10: 73m1903c evaluation board silk screen top ....................................................................... 18 figure 11: 73m1903 c evaluation board top signal layer ..................................................................... 19 figure 12: 73m1903c evaluation board layer 2 C ground plane ........................................................... 19 figure 13: 73m1903c evalua tion board layer 3 C supply plane ............................................................ 20 figure 14: 73m1903c evaluation board bottom signal layer ................................................................ 20 tables table 1: 73m1903c register memory map .............................................................................................. 9 table 2: control register settings for example sample rates ............................................................... 11 table 3: 73m1903c evalu ation board connectors ................................................................................. 12 table 4: jp25 pin assignments ............................................................................................................. 13 table 5: 73m1903c evaluation board jumper description ..................................................................... 13 table 6: 73m1903c evaluation board bill of materials ........................................................................... 21 downloaded from: http:///
um_1903c_030 73m1903c evaluation board user manual rev. 2.0 5 1 introduction the t eridian semiconductor corporation (tsc) 73 m1903c evaluation board is a modem analog front end e valuation bo ard with an on - board daa for evaluating the 73m1903c device. this device can support up to v.90 modulation and demo dulation on typical dsp or cpu systems available in the market. the 73m1903c evaluation board incorporates a 73m1903c integrat ed circuit, a us, ctr21 or world wide daa circuit for interfacing with the telephone line and an audio amplifier and speaker for line monitoring during the call progress period. the evaluation b oard supports the evaluation of the 73m1903c modem analog fro nt end device for universal modem application s and interface s to a general purpose dsp or cpu system. figure 1 : 73 m1903c evaluation board 1.1 safety and esd note s the 73m1903c evaluation board is esd sensitive! esd precautions should be taken when handling the evaluation board! 1.2 evaluation board host interfaces the 73m1903c evaluation board includes a modem analog front end (mafe ) interface with a 20 - pin right angle connector to connect to a target dsp or cpu system. the evalu ation b oard also includes a 3.3 v power receptacle for powering the on board circuits from either the target system or an external power supply. downloaded from: http:///
73m1903c evaluation board user manual um_1903c_030 6 rev. 2.0 2 system description figure 2 shows a block diagram of the 73m1903c e valuation board. this section includes descriptions of: ? modem analog front e nd (mafe) host system interface ? 73m1903c r egister map ? system initiali zation 73 m 1903 c sclk fsb fsbd sdin txap 1 txan 1 txap 2 txan 2 rxap rxan daa gpio 5( oh ) gpio 4( ring ) sdout phone line power supply reset power amp speaker volume control gpio0 gpio1 gpio2 xtal 73 m 1903 c evaluation board figure 2 : 73 m1903c evaluation board block diagram downloaded from: http:///
um_1903c_030 73m1903c evaluation board user manual rev. 2.0 7 2.1 mafe interface the modem analog front end (mafe) interface is a serial port integrated into the 73m1903c device to interface to a host controller or a dsp. this serial data port is a bi - directional port that is supported by most dsps available in the market. the mafe interface requires one end to act as a master and the other as a slave. the 73m1903c device can be configured either as a master or as a slave (refer to figure 3 ). multiple 73m1903c devices can also be daisy chained in a single master and multiple slave configuration (refer to figure 4 ). sclk fsb oscin sdin sdout 73 m 1903 c ( master ) sckmod "1/0" fsb sclk sdin sdout mclk host sclk fsb oscin sdin sdout 73 m 1903 c ( slave ) sckmod "x" fsb sclk sdin sdout host 73 m 1903 c master mode 73 m 1903 c slave mode ( master ) ( slave ) figure 3 : 73m1903c in master or slave configuration sclk fsb oscin sdin sdout 73 m 1903 c ( master ) sckmod "1/0" fsb sclk sdin sdout mclk host sclk fsb oscin sdin sdout 73 m 1903 c ( slave ) sckmod "x" fsbd sclk fsb oscin sdin sdout 73 m 1903 c ( slave ) sckmod "x" fsb sclk sdin sdout host sclk fsb oscin sdin sdout 73 m 1903 c ( slave ) sckmod "x" fsbd daisy chain for master / slave mode daisy chain for slave mode ( slave ) ( master ) figure 4 : 73m1903c daisy chain configurations figure 5 and figure 6 show the mafe and serial data timing diagrams. downloaded from: http:///
73m1903c evaluation board user manual um_1903c_030 8 rev. 2.0 tx 15 tx 14 tx 13 tx 12 tx 11 tx 10 tx 9 tx 8 tx 7 tx 6 tx 5 tx 4 tx 3 tx 2 tx 1 tx 0 rx 15 rx 14 rx 13 rx 12 rx 11 rx 10 rx 9 rx 8 rx 7 rx 6 rx 5 rx 4 rx 3 rx 2 rx 1 rx 0 sclk sdout sdin fsb data frame with frame sync r/w a6 a5 a4 a3 a2 a1 a0 di 7 di 6 di 5 di 4 di 3 di 2 di 1 di 0 0 0 0 0 0 0 0 0 do 7 do 6 do 5 do 4 do 3 do 2 do 1 do 0 control frame data format sdout sdin fsb sclk figure 5 : mafe timing diagram sclk sdout sdin fsb txd rxd ctrl - di ctrl - do txd rxd ctrl - di ctrl - do control frame data frame one sample period control frame data frame sclk sdout sdin fsb txd rxd txd rxd ctrl - di ctrl - do d0=0 d0=1 txd rxd txd rxd d0=0 hardware controlled control frame software controlled control frame one sample period figure 6 : s erial data timing downloaded from: http:///
um_1903c_030 73m1903c evaluation board user manual rev. 2.0 9 2.2 73m1903c register map table 1 shows the memory map of the addressable registers in the 73m1903c. each register can be read or written by a host controller or a dsp using the mafe interface contr ol frame format. all registers and their bits are described in detail in the 73m1903c d ata s heet . table 1 : 73m1903c register memory map address default b it 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 0x08 enfe seltx2 txbs t1 txbst0 txdis rxg1 rxg0 rxgain 0x01 0x00 tmen diglb analb intlb ckouten rxpull spos hc 0x02 0x ff gpio7 gpio 6 gpio 5 gpio 4 gpio 3 gpio 2 gpio 1 gpio 0 0x03 0x ff dir7 dir6 dir5 dir4 dir3 dir2 dir1 dir0 0x04 0x00 reserved reserved reserved reserved re served reserved reserved reserved 0x05 0x00 reserved reserved reserved reserved reserved reserved reserved reserved 0x06 0x50 rev3 rev2 rev1 rev0 fsbden trim(2) trim(1) trim(0) 0x07 0x00 unused testpll tclksel1 tclksel0 atx dtx arx drx 0x08 0x00 pseq7 pseq6 pseq5 pseq4 pseq3 pseq2 pseq1 pseq0 0x09 0x0a prst2 prst1 prst0 pdvsr4 pdvsr3 pdvsr2 pdvsr1 pdvsr0 0x0a 0x22 ichp3 ichp2 ichp1 ichp0 fl kvco2 kvco1 kvco0 0x0b 0x12 unused ndvsr6 ndvsr5 ndvsr4 ndvsr3 ndvsr2 ndvsr1 ndvsr0 0x0c 0x00 nseq7 nseq6 nseq 5 nseq4 nseq3 nseq2 nseq1 nseq0 0x0d 0x c0 xtal1 xtal0 lokdeten thlk0 unused nrst2 nrst1 nrst0 0x0e 0x00 frcvco pwdnpll lokdet unused unused unused unused unused 2.3 73m1903c system initialization the following example shows the sequence to follow to bring the 73m1903c device out of reset and to start up after power up. the 73m1903c device does not have a power on reset circuit . for proper operation, a reset signal must be asserted from the host by pulling the 73m1903c reset pin low for approximately 100 ns or longer after the power is stabilized. the 73m1903c device will be ready to use within 100 s after the removal of the reset pulse from the reset pin. reset the 73m1903 d evice 1. power up the system . 2. wait for the 3.3 v power to be come stable . 3. hold the 73m1903c reset pin low for 100 ns or longer then let it go h igh . 4. wait for 100 s for the pll and o sc to be stabilized . initialize the 73m1903 device there are control opera ting modes; hardware control and software control. in the hardware control mode , th e serial interface will alternate between data frames and control frames. if synchronization is lost and it is not known whether a data or control frame is being sent, it is necessary to reini tialize the hc mode. since there isnt way to initially tell the difference between whether a control frame or data frame is being sent, it is necessary to send a reset of this bit in two consecutive frames, and the procedure for this is as follows: a. f rame synchronization 1. r eset the hc bit (reg ister 0x 01 bit 0) in a fra me sequence . downloaded from: http:///
73m1903c evaluation board user manual um_1903c_030 10 rev. 2.0 2. r eset the hc bit ( reg ister 0x 01 bit 0) in next frame sequence . at this point, the 73m1903c is guaranteed to be in the software controlled control frame mode . all the mafe serial data will be data only unless the host request s a control frame by setting the lsb of the tx data to a one by setting bit 0 of data frame . the following frame will then be a control frame. b. control frame generation ? s oftware controlled control frame 1. m ask txd bit 0 as 1 to request a subsequent control frame. 2. write or read the 73m1903c register using the mafe control data format. 3. make sure to m ask txd bit 0 as 0 if the control frame is not needed. ? hardware controlled control frame 1. m ask txd bit 0 as 1 to request a subsequent control frame. 2. s et the hc bit (reg ister 0x 0 1 bit 0) using the mafe control data format in the next frame. from this point on, there will be alternating data and control frames . make sure not to miss this sequence. this is needed to initialize the hc mode. example 1: using the s oftware c ontrolled c ontrol f rame: static const u16 init_afe_config[] = // must have data(lsb=1), control, data(lsb=1), control,.. frame s { ctrl2|0x00, ctrl2|0x00, // force to software controlled control frame ctrl_frame, ctrl13|0x00, // force to xtal clock ctrl_frame, ctrl1|enfe, // enable analog ctrl_frame, ctrl2|0x00, // ctrl_frame, gpio|0x00, // ctrl_frame, gdir|0xd0, // gpio 7,6,4=in 5,3,2,1,0=output ctrl_frame, gie|0x00, ctrl_frame, gip|0x00, ctrl_frame, bgtrim|0x00, ctrl_frame, test|0x00, ctrl_frame, ctrl08|afe_ctrl08, // timing chain set up ctrl_frame, ctrl09|afe_ctrl09, ctrl_frame, ctrl10|afe_ctrl10, ctrl_frame, ctrl11|afe_ctrl11, ctrl_frame, ctrl12h|afe_ctrl12h, ctrl_frame, ctrl12l|af e_ctrl12l, ctrl_frame, rwb|gpio, // delay for 2 sample cycle time to ctrl_frame, rwb|gpio, // let pll settle before lockdet ctrl_frame, ctrl13|afe_ctrl13 }; note: ctrl_frame = 0x0001 example 2: using the a utomatic c ontrol f rame ( h ardware controlled control frame) static const u16 init_afe_config[] = // must have dummy data, control, dummy data, control,.. frames { ctrl2|0x00, ctrl2|0x00, // force to software controlled control frame ctrl_frame, ctrl13|0x00, // force to xtal cl ock ctrl_frame, ctrl1|enfe|hc, // enable analog 0x0000, gpio|0x00, // forces data to be 0x0000 0x0000, gdir|0xd0, // gpio 7,6,4=in 5,3,2,1,0=output downloaded from: http:///
um_1903c_030 73m1903c evaluation board user manual rev. 2.0 11 0x0000, gie|0x00, 0x0000, gip|0x00, 0x0000, bgtrim|0x00, 0x0000, test|0 x00, 0x0000, ctrl08|afe_ctrl08, // timing chain set up 0x0000, ctrl09|afe_ctrl09, 0x0000, ctrl10|afe_ctrl10, 0x0000, ctrl11|afe_ctrl11, 0x0000, ctrl12h|afe_ctrl12h, 0x0000, ctrl12l|afe_ctrl12l, 0x0000, rwb|gpio, // dela y for 2 sample cycle time to 0x0000, rwb|gpio, // let pll settle before lockdet 0x0000, ctrl13|afe_ctrl13 }; 2.4 typical sample rate settings table 2 shows the register values to set up for each example sample rate using a 24.576 mhz crystal. table 2 : control register settings for example sample rates register (addr) sample rate 7.2 k hz 8 k hz 9.6 k hz 14.4 k hz 16 k hz ctrl08 ( 0x08) 0x00 0x00 0x00 0x00 0x00 ctrl09 ( 0x09) 0x0a 0x0a 0x0a 0x0a 0x08 ctrl10 (0x 0a) 0x10 0x11 0x22 0x26 0x17 ctrl11 (0x 0b) 0x0d 0x0f 0x12 0x1b 0x18 ctrl12h ( 0x 0c) 0x02 0x00 0x00 0x00 0x00 ctrl12l ( 0x 0d) 0x c1 0x c0 0x c0 0x c0 0x c0 downloaded from: http:///
73m1903c evaluation board user manual um_1903c_030 12 rev. 2.0 3 hardware description 3.1 board settings: jumpers and connectors figure 7 shows all the connectors and jumpers avail able on 73m1903c evaluation board . j7 jp12 -- jp23 jp 1 -- jp11 jp25 js 1 j6 j4 j5 jp24 j1 j3 j2 figure 7 : 73m1903c evaluation board jumpers and connectors ta ble 3 lists the evaluation board connectors. js1 is the main connector for interfacing to a host processor or dsp board. the pins of this connector are configurable by jumper setting s (jp1 to jp24). table 5 des cribes the details of the jumper settings. j6 is a modular connector for connection to the telephone line and j7 is for power connection from the main board or from an external power supply. jp25 is an alternative mafe interface connector whose pin assignments are show in table 4. table 3 : 73m1903c evaluation board connectors schematic and pcb r eference name description js1 conn socket 10x2 20 - pin connector to interface the 73m1903c e valuation board to a host controller main board . j6 rj - 11 telephone line connector . j7 3.3v external supply plug for connecting external 3.3 v dc power supply. jp25 header 5x2 10 pin interface connector / mafe test points . downloaded from: http:///
um_1903c_030 73m1903c evaluation board user manual rev. 2.0 13 table 4 : jp25 pin assignments pin# name pin# name 1 nc (sclk in slave mode) 6 sclk 2 ringd 7 afein 3 hook 8 afeout 4 fsb 9 reset 5 fsbd 10 gnd table 5 : 73m1903c evaluation board jumper description schematic and pcb r eference na me description jp1 jumper strap two - pin header that allows js1 pin 1 to be assigned as fsbd. shunt: js1 pin1 = fsbd open: js1 pin 1 is floating jp2 jumper strap two - pin header that allows js1 pin 4 to be assigned as afein. shunt: js1 pin4 = afein ope n: js1 pin 4 is controlled by jp13 jp3 jumper strap two - pin header that allows js1 pin 5 to be assigned as afeout. shunt: js1 pin 5 = afeout open: js1 pin 5 is floating jp4 jumper strap two - pin header that allows js1 pin 7 to be assigned as fs. shu nt: js1 pin 7 = fs open: js1 pin 7 is controlled by jp15 jp5 jumper strap two - pin header that allows js1 pin 9 to be assigned as fs. shunt: js1 pin 9 = fs open: js1 pin 9 is controlled by jp16 jp6 jumper strap two - pin header that allows js1 pin 11 t o be assigned as afeout. shunt: js1 pin11 = afeout open: js1 pin 11 is floating jp7 jumper strap two - pin header that allows js1 pin 15 to be assigned as afein. shunt: js1 pin 15 = afein open: js1 pin 15 is controlled by jp19 jp8 jumper strap two - pi n header that allows js1 pin 16 to be assigned as afeout. shunt: js1 pin 16 = afeout open: js1 pin 16 is floating jp9 jumper strap two - pin header that allows js1 pin 17 to be assigned as afein. shunt: js1 pin 17 = afein open: js1 pin 17is controlled b y jp20 jp10 jumper strap two - pin header that allows js1 pin 18 to be assigned as fs. shunt: js1 pin 18 = fs open: js1 pin 18 is floating jp11 jumper strap two - pin header that allows js1 pin 20 to be assigned as d igital s ignal ground. shunt: js1 pin 2 0 =gnd open: js1 pin 20 is floating jp12 jumper strap two - pin header that allows js1 pin 2 to be assigned as vccd (3.3 v digital supply) . shunt: js1 pin 2 = vccd open: js1 pin 2 is floating downloaded from: http:///
73m1903c evaluation board user manual um_1903c_030 14 rev. 2.0 schematic and pcb r eference na me description jp13 jumper strap two - pin header that allows js1 pin 4 to be assigned as reset. shunt: js1 pin 4 = reset open: js1 pin 4 is controlled by jp2 jp14 jumper strap two - pin header that allows js1 pin 6 to be assigned as sclk. shunt: js1 pin 6 = sclk open: js1 pin 6 is floating jp15 jumper strap two - pin header th at allows js1 pin 7 to be assigned as reset. shunt: js1 pin 7 = sclk open: js1 pin 7 is controlled by jp4 jp16 jumper strap two - pin header that allows js1 pin 9 to be assigned as ringd. shunt: js1 pin 9 = ringd open: js1 pin 9 is controlled by jp5 jp17 jumper strap two - pin header that allows js1 pin 10 to be assigned as hook. shunt: js1 pin 10 = hook open: js1 pin 10 is floating jp18 jumper strap two - pin header that allows js1 pin 13 to be assigned as hook. shunt: js1 pin 13 = hook open: js1 pin 13 is floating jp19 jumper strap two - pin header that allows js1 pin15 to be assigned as ringd. shunt: js1 pin 15 = ringd open: js1 pin 15 is controlled by jp7 jp20 jumper strap two - pin header that allows js1 pin 17 to be assigned as sclk. shunt: js1 pin 17 = sclk open: js1 pin 17 is controlled by jp9 jp21 testb two - pin header that selects factory test. this pin must be left open for normal operation. jp22 clkmode two - pin header that selects the 73m1903c clock mode. shunt: 73m1903c 32 clock p er frame open: 73m1903c continuous clock mode jp23 jumper strap two - pin header to select slave mode. shunt: 73m1903c master configuration. (r8 must be depopulated) open: 73m1903c slave configuration (r8 must be populated) jp24 jumper strap two - pin header to enable daisy chaining. shunt: 72m1903c fsbd signal is connected to jp2 5 pin3 and js1 pin through jp1 (daisy chain enable) open: 73m1903c fsbd pin is isolated (no daisy chain ) j1, j2, j3 speaker volume control three - pin header for selecting the line monitor speaker volume. manual volume control: j1 j2 j3 volume control 1-2 dont care dont care shutdown (mute) open 1-2 1-2 6 db amp gain open 1-2 open 12 db amp gain open open 1-2 18 db amp gain open open open 23.4 db amp gain downloaded from: http:///
um_1903c_030 73m1903c evaluation board user manual rev. 2.0 15 schematic and pcb r eference na me description software v ol ume control by the 73m1903c gpio: t he 73m1903c gpio 0 , 1 and 2 must be configured as output) . j1(2 - 3), j2(2 - 3), j3(2 - 3) gpio2 gpio1 gpio0 volume control low dont care dont care shutdown (mute) high low low 6 db amp gain high low high 12 db amp gain high high low 18 db amp gain high high high 23.4 db amp gain j4 ring detector output three - pin header that selects the ring d etector output to connect to either gpio4 of the 73m1903c or to a host cpu gpio through js1 or jp25. 1- 2: ring d etector output is fed to 73m1903c gpio4 (gpio4 must be configured as an input ). 2- 3: ring detector output is directed to a host controller through either js1 or jp25 . j5 off - hook control three - pin header that selects the off - hook control by either 73m1903c gpio5 or by a host cpu gpio through js1 or jp25. 1- 2: off - hook is controlled by 73m1903c gpio5 (gpio5 must be configured as an output). 2- 3: off - hook is controlled by a host output through either js1 or jp25. downloaded from: http:///
73m1903c evaluation board user manual um_1903c_030 16 rev. 2.0 3.2 board physical and operating information pwr rj11 20 p conn trans spk 4.00 2.15 0.69 0.62 1.17 1.18 0.27 0.35 0.33 0.20 0.15 figure 8 : 73m1903c evaluation board pcb dimensions pcb dimensions ? size 4.00 x 2.15 (101.60 x 54.60 mm) ? height with components and solder 0.65 (16.5 mm) environmental ? operating temperature - 40 c to +85 c ( crystal oscillator function is affected outside C 10 c to +60 c range ) ? storage temperature - 65 c to 150 c power supply ? dc input voltage (powered from dc supply) 3.3 vdc 0.5 v ? supply current 25 ma (off - hook at room temperature) typical downloaded from: http:///
um_1903c_030 73m1903c evaluation board users manual rev. 2.0 17 4 73m1903c evaluation board schematics, pcb layouts and bill of materials 4.1 schematic hook afeout sclk + c19 3.3uf c22 0.1uf c18 0.1uf - + u4 hd04 3 1 4 2 vccd r21 150k js1 conn socket 10x2 3m 5120-b7a2jl 2 2 4 4 6 6 8 8 10 10 12 12 14 14 1 1 3 3 5 5 7 7 9 9 11 11 13 13 15 15 16 16 17 17 18 18 19 19 20 20 vcca vccd ringd ringd j7 power connector o 1 i 3 s 2 r6 150k tp15 ti p 1 tp16 ring 1 reset tp2 r xa n 1 tp4 txa n 2 1 tp5 tran1 1 tp14 tran2 1 tp13 r xa p 1 tp10 txap2 1 jp13 sclk fs afeout reset afein fsbd c28 0.47uf 200v c13 .082uf c27 0.47uf 200v r15 20k r8 4.7k nc afein slave mode: populate r8 w ith a 4.7k resistor master mode: do not populate r8 slave mode: open jp23 master mode: shunt jp23 vccd e1 p3100sc teccor sidactor jp18 r29 20k f1 tr600-150 raychem poly switch cid coupling defa ult setting: shunt jp7, jp8, jp10, jp11, jp20, jp22 r33 9.1k r49 9.1k of f hook control ringb hook ring detection jp19 this version supports: ---ring detection ---caller id d4 1n4001 2 1 hook j6 rj-11 1 2 3 4 5 6 sclkmode open options: js 1 - redw ood 5 connector 20 pin rt. angle socket shunt jp7,jp8, jp10, jp11, jp20, jp22 and install r48, r49. use sumida mit 4033 transformer energy ring detection: remove u3, d4, d2, d3, r29, r33 and replace c25 and c26 w ith 0.22uf mode0 open r11 374 r20 374 c7 150n + c1 3.3uf c3 0.1uf jp7 + c15 10uf c20 0.1uf d1 bzt52c15-7 slave mode: shunt jp14, jp1 master mode: open jp14, jp1 jp16 r50 4.7k t1 transformer_0 sumida 3a 2a 4a 1a 1b 2b 3b 4b r52 0 r51 0 vccd jp17 vcca slave mode: populate r31 w ith 0 ohm master mode: do not populate r31 jp10 u2 73m1903c-32_0 vnd 1 vpd 2 gpio0 3 gpio1 4 gpio2 5 gpio3 6 fs 7 sclk 8 vpa 9 txa n 1 10 txa n 2 11 txap1 12 txap2 13 r xa n 14 r xa p 15 vna 16 vnpll 17 xout 18 xin 19 vppll 20 fsbd 21 vnd 22 gpio4 23 gpio5 24 vpd 25 rst 26 test 27 sckmode 28 sdin 29 gpio6 30 gpio7 31 sdout 32 c6 150n c23 150n jp11 j2 header3 1 2 3 j3 header3 1 2 3 j1 header3 1 2 3 r5 4.7k r9 4.7k jp15 tp11 gnd 1 q2 mmbta42l offhook ring detector c29 0.047u shutdown jp3 gain1 gain0 jp4 manual volume control: j1 (1-2) , j2/j3(don't care):shutdow n (mute) j1(open), j2((1-2),j3(1-2) : 6db amp gain j1(open), j2((1-2),j3(open) : 12db amp gain j1(open), j2((open),j3(1-2) : 18db amp gain j1(open), j2((open),j3(open) : 23.4db amp gain. softw are volume control: j1(2-3), j2(2-3) and j3(2-3). jp24 r10 49.9 jp5 jp1 r30 56k tp1 gpio0 1 c12 1uf c4 0.1uf jp6 c5 1uf c9 10uf r1 120k r2 120k c11 220pf r3 120k u1 tpa2001d1 inp 1 inn 2 shdn 3 gain0 4 gain1 5 pvdd 6 ou tp 7 pgnd 8 pgnd 9 ou tn 10 pvdd 11 vdd 12 rosc 13 cosc 14 agnd 15 by p 16 c2 1uf c10 1uf ls1 intervox bst1811p-06 1 2 3 ring path r12 120k c8 0.1uf cid coupling d3 22v 2 1 vccd d2 22v 2 1 vccd vcca slv_clk jp9 r48 100 jp20 r24 18 q1 fzt605ct 1 3 2 4 + c16 10uf 25v tp3 txa n 1 1 tp12 txap1 1 r22 62k r17 33k + c24 3.3uf 25v slv_clk jp14 c14 3.3uf c17 3.3uf dial pulse shaper this block must be isolated from the main power/ground plane. vccd fs u3 tlp627 1 2 4 3 fs jp8 sclk tp9 gpio6 1 tp6 gpio7 1 vccd jp12 jp21 gated sck 1 2 jp22 mode 0 1 2 vccd tp8 reset 1 y1 24.576m c25 33pf c26 22pf fsbd l4 nlc322522t-4r7m jp2 tp7 fsbd 1 l1 nlc322522t-4r7m l2 nlc322522t-4r7m l3 nlc322522t-4r7m j5 header3 1 2 3 u5 tlp627 1 2 4 3 j4 header3 1 2 3 default setting: shunt j23 and remove r8. tp18 gnd 1 r13 210 r16 210 default setting: do not populate r52 r4 48.7k r14 150k r23 48.7k r18 150k c21 150n jp23 r19 49.9 jp25 header 5x2 1 2 3 4 5 6 7 8 9 10 figure 9 : 73 m1903c evaluation board electrical schematic downloaded from: http:///
73m1903c evaluation board user manual um_1903c_030 18 rev. 2.0 4.2 pcb layouts figure 10 : 73m1903c evaluation board s ilk screen top downloaded from: http:///
um_1903c_030 73m190 3c evaluation board user manual rev. 2.0 19 figure 11 : 73 m1903c evaluation board top signal layer figure 12 : 73m1903c evaluation board layer 2 C ground plane downloaded from: http:///
73m1903c evaluation board user manual um_1903c_030 20 rev. 2.0 figure 13 : 73m1903c evaluation board layer 3 C supply plane figure 14 : 73m1903c evaluation board bottom signal layer downloaded from: http:///
um_1903c_030 73m190 3c evaluation board user manual rev. 2.0 21 4.3 bill of materials table 6 provides the bill of materials for the 73m1903c evaluation board schematic provided in figure 9 . table 6 : 73m1903c evaluation board bill of materials item qty. reference part manufacturer 1 4 c1, c14, c17, c19 3.3 f panasonic 2 4 c2, c5, c10, c12 1 f panasonic 3 6 c3, c4, c8, c18, c20, c22 0.1 f panasonic 4 4 c6, c7, c21, c23 150 nf (0.15 f) panasonic 5 2 c9,c15 10 f panasonic 6 1 c11 2 nf (0.002 f ) panasonic 7 1 c13 0.082 f panasonic 8 1 c16 3.3 f 16 v / 25 v kemet 9 1 c24 10 f 16 v / 25 v panasonic 10 1 c25 33 pf panasonic 11 1 c26 22 pf panasonic 12 2 c27, c28 0.47 f 250 v utc 13 1 c29 0.047 f 50 v panasonic 14 2 d1 15 v / mmsz15t1 on semiconductor 15 2 d3, d2 22 v/ mmsz5 251bdict diodes 16 1 d4 s1g diodes 17 1 e1 p3100sc teccor 18 1 f1 tr600 - 150 raychem 19 24 jp1 C jp24 2 pin header sullin 20 1 jp25 header 5x2 sullin 21 1 js1 conn socket 10x2 3m 22 5 j1, j2, j3, j4, j5 3 pin header sullin 23 1 j6 rj - 11 amp/tyco 24 1 j7 power connector switchcraft 25 1 ls1 speaker/at - 2308 intervox 26 4 l1, l2, l3, l4 nlc322522t - 4r7m tdk 27 1 q1 fzt605 zetex i nd. 28 1 q2 mmbta42 on semiconductor 29 4 r1, r2, r3, r12, 120 k panasonic 30 2 r23, r4 48.7 k panasonic 31 3 r5, r9, r50 4.7 k panasonic 32 4 r6, r14, r18, r21 150 k panasonic 33 2 r19, r10 49.9 panasonic 34 2 r11, r20 374 panasonic 35 2 r13, r16 210 panasonic 36 2 r15,r29 20 k panasonic 37 1 r17 33 k panasonic 38 1 r22 62 k panasonic 39 1 r24 18 ? w panasonic 40 2 r33, r49 9.1 k panasonic 41 1 r30 56 k panasonic 42 1 r48 100 panasonic downloaded from: http:///
73m1903c evaluation board user manual um_1903c_030 22 rev. 2.0 item qty. reference part manufacturer 44 1 r51, r52 0 panasonic 45 17 tp1 C tp18 test point sullin 46 1 t1 emit4033l sumita 47 1 u1 tpa2001d1 ti 48 1 u2 73m1903c - 32 teridian 49 2 u3, u5 tl p627 toshiba 50 1 u4 h04 diodes 51 1 y1 24.576 mhz ecs inc downloaded from: http:///
um_1903c_030 73m190 3c evaluation board user manual rev. 2.0 23 5 ordering information part description order n umber 73m1903c evaluation board with worldwide and 600 ? termination 73m1903c - evm 6 related documentation the following 73m1903c documents are available from teridian semiconductor corporation: 73m1903c data sheet 7 contact information for more information about teridian semiconductor products or to check the availabili ty of the 73 m1903c contact us at: 6440 oak canyon road suite 100 irvine, ca 92618 - 5201 telephone: (714) 508 - 8800 fax: (714) 508 - 8878 email: modem .support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com . revision history revision date description 1.0 11/12/2004 first release. 2.0 6/12 /2009 revised in new format. downloaded from: http:///

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